The electronics industry continues to rely upon advances in semiconductor manufacturing technology to realize higher-functioning devices while improving reliability and cost. For many applications, the manufacture of such devices is complex, and maintaining cost-effective manufacturing processes while concurrently maintaining or improving product quality is difficult to accomplish. As the requirements for device performance and cost become more demanding, realizing a successful manufacturing process becomes more difficult.
Indeed, as the level of integration of the circuits increases, the devices become smaller and more densely packed, requiring more levels of photolithography and more processing steps. As more layers are built upon the silicon starting wafer, problems caused by surface non-planarity become increasingly severe and can impact yield and chip performance. In fact, it becomes more and more necessary to remove excess material from the wafer in a process commonly referred to as planarization (or, at times, “polishing”).
A common technique used to planarize the surface of a silicon wafer is chemical mechanical planarization (CMP). CMP involves the use of a polishing pad affixed to a polishing table and a separate holder to present the silicon wafer face-down against the pad surface. A slurry containing abrasive and chemical additives is dispensed onto the surface of the polishing pad and used to remove irregularities from the surface of the wafer through both mechanical and chemical means. An extension of this CMP process, referred to as ECMP, involves the use of electrical energy so as to remove unwanted material cathodically via an electrolyte. The polishing pad itself is typically chosen for its ability to act as a carrier of the slurry (or electrolyte) as well as its ability to provide the desired mechanical force against the wafer surface being polished.
The wafer and polishing pad commonly rotate relative to each other. The rotation action, along with the abrasive and chemical additives of the slurry, results in a polishing action that removes material from the surface of the wafer. Protrusions on the surface erode more efficiently than recessed areas, leading to a flattening—or planarization—of the wafer surface.
As the length of time a wafer is polished increases, and/or the number of wafers that have been polished increases, the polishing pad will become filled with debris as a result of the accumulation of removed wafer material, chemical reaction by-products and abrasives from the slurry. This deposited debris causes the polishing pad to become matted down and/or wear unevenly, also known as the “glazing effect”. Thus, it becomes necessary to restore the polishing pad to a state suitable for continued wafer polishing.
“Pad conditioning” or “pad dressing” is a process known in the art that is used to restore the surface of the polishing pad and remove the glazing by dislodging particulates and spent polishing slurry from the pad. Pad conditioning also planarizes the pad by selectively removing pad material, and roughens the surface of the polishing pad. Pad conditioning may be performed “ex-situ” (i.e., conditioning the polishing pad between wafer polishing cycles), or “in-situ” (i.e., concurrent with, or during, the wafer polishing cycle). In a typical prior art “in-situ” pad conditioning process, a fixed abrasive disk is brushed along the pad surface to remove a small amount of pad material and debris, thus creating new asperities for allowing the polishing slurry to flow freely. The removed pad material and debris then combine with the slurry flow stream of the polishing process, and are passively carried away from the pad and the wafer being polished by normal slurry transport mechanics. Ultimately, these materials are flushed at the end of the polishing cycle with rinse water, and collected in the central drain of the polisher.
As different materials come into use for integrated circuit fabrication, the CMP process must keep pace in its ability to react with and planarize these different materials. For example, copper has become an increasingly popular choice for interconnect metal and has begun replacing aluminum and/or tungsten in certain applications. Copper is much more conductive than these other metals, allowing the formation of finer wires having lower resistive losses. Although copper provides advantages over aluminum, it has at least one major disadvantage: copper is specifically adverse to silicon, since it readily diffuses into silicon and results in deep-level defects. Therefore, copper must be isolated from silicon during the formation of integrated circuit devices, usually through the use of a suitable “barrier” layer metal. A metal CMP process thus requires the implementation of a multi-step planarization process, using different polishing slurries and/or parameters to remove different surface materials. For example, in copper CMP, one chemistry is required to remove the non-planar copper and another chemistry to remove the barrier material. In the past, a first polishing station may have been set up to remove the bulk copper, a second polishing station to remove the barrier material, and a third station to perform a final buffing operation, since cross-contamination from the different polishing agents would invariably occur if only a single station were to be used.
With respect to conventional, dielectric CMP, some manufactures suggest the use of multiple polishing stations, with “partial polishing” processes being performed at each station. For example, a first station would be used to perform an initial planarization (perhaps time dependent) to remove bulk unwanted material, a second station to finish the planarization and a third station to perform a buffing operation. Each of these stations may utilize the same polishing chemistry, but would employ different techniques for process control (downforce, speed, endpoint detection, etc.). The use of multiple stations in this case improves the throughput for the CMP system, since each polishing step is shorter, but the improvement in throughput is achieved at the risk of three separate wafers/polishing supplies/stations needing to simultaneously be involved in the fabrication process.
Thus, even though the use of multiple polishing stations may provide process improvement for CMP systems, such an arrangement becomes extremely time-consuming, capital intensive and expensive. A need remains in the art, therefore, for an arrangement for performing a multi-step polishing process in a CMP system that requires the use of only a single polishing station.